96P TCAT tear down report from TechInsightsģD NAND is a type of non-volatile flash memory in which the memory cells are stacked vertically in multiple layers.64P TCAT tear down report from TechInsights.32P TCAT tear down report from TechInsights.Method of making three-dimensional NAND memory. Mokhlesi N, Scheuerlein R, inventors SanDisk 3D LLC, assignee.Moore, “Cramming More Components onto Integrated Circuits”, Electronics Magazine, vol. The SEMulator3D virtual fabrication platform provided increased understanding and visibility into these complex 3D NAND integration schemes and their resulting 3D structures, along with a time and cost-efficient optimization methodology. In this study, we have used SEMulator3D to create process models of 3D NAND split and staircase patterning schemes. The depth should be complementary on any two sides containing the same Y coordinate, so that a particular wordline can be selected on a particular side. The stair stack split step is designed to split ON pairs into 4 different depths in the right and left side of the cell area. We assume that the bitline is oriented in the Y direction while the wordline is oriented in the X direction. Therefore, it is possible to use a split mask combined with a trim process to split 4 stacks from a single stack before the main staircase etch process.įigure 5displays a potential split and stair layout design using a 64P process. Lithography using thick resists and trim step etching have been widely adopted in staircase formation. Traditionally, to split 4 stacks from a single stack, 2 masks would be necessary. In the 64P and 96P processes, each staircase includes 4 pairs of wordline metal in the cross bitline direction, highlighting that extra mask and process steps are necessary to split these 4 stacks from a single stack in the bit line direction. 2), each wordline metal was assigned to a single step in the cross bitline direction. Each wordline metal layer is also split at each staircase. In 3D NAND, wordline metal is connected to BEOL metal through the stair contact in the staircase area.
Patterning Scheme Analysis of the Staircase
Furthermore, the replacement metal gate process is much more challenging, due to a larger lateral etch and deposition distance. Unfortunately, these benefits have an extra cost in additional processes and masks. The physical structure is also much stronger, since only 3 layers are cut by the mini slit and 9 channel holes are supported between two deep slits.With a dummy channel hole and mini slit, channel hole patterning is more uniform and there is decreased loading of the channel hole CD and depth.The mini slit has a smaller CD and less space between neighboring channel holes than a larger normal slit, saving area in the bit line direction.The introduction of a mini slit provides three benefits: With the combination of bit lines, word lines and string select lines, 1 of 9 memory cells can be exclusively addressed using the mini slit and two larger normal slits. The mini slit divides the top 3 ON stacks into 2 sides, with the left and right sides connected to separate string select lines. At the 64P and 96P process nodes, an extra mini slit process is introduced to cut the center dummy channel hole and effectively split 9 holes into 4 holes on each side. Patterning Scheme Analysis of Extra Mini SlitĪt the 32P TCAT process node, 1 of 4 memory cells can be exclusively addressed between any two slits using a combination of bitlines and wordlines. Enhancing device density without sacrificing the allowed process window is a key issue in 3D NAND process development.
TURBOBLEND SHATTER DABBLE EXTRACTS WINDOWS
These narrower process windows are needed so that the downstream stair contact will precisely land on the staircase center without shorting the word line at the stair sidewall. Also, shrinking the stair CD and pitch will require a more uniform stair angle along with a much smaller CD variation in the stair etch process. With a smaller channel hole pitch and CD, the allowed process window for other processes (such as the channel hole to channel hole bridge during the etch process, or the channel hole to substrate open in both the etch and deposition processes) will become narrower. For example, if the slit pitch is reduced, the channel hole pitch must also be decreased at the same time. Unfortunately, these changes can introduce many challenges in lithography and downstream etch and gap filling processes. Traditionally, memory cell and staircase area could be reduced by decreasing the CD and pitch of the slit and stair structures. In 3D NAND, slit pitch in the bitline direction, and stair pitch in the cross bitline direction, are two of the most important factors in determining memory cell and staircase area. The Effect of Patterning Schemes on the Process Window
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